Solid state imaging arrays are semiconductor devices which are used to convert an optical image into an electrical signal. The light-sensitive semiconductor surface is arranged in a matrix of picture elements called pixels, each including a photodetector in which electrical charges are introduced when light from a scene is focused on the surface of the device. Photons striking the surface of the photodetector generate free electrons in an amount linearly proportional to their radiant energy. Hence, the amount of charge collected as a charge packet in the photodetector will be a faithful representation of the intensity of the image at that pixel location. These charge packets are then periodically transferred into a CCD shift register.
When the charge packets are introduced into the CCD, they are stored in a spatially-defined depletion region, or potential well. The potential well is located either at or under the surface of the semiconductor device, depending upon the type of CCD technology used. In a surface channel CCD, minority charge is stored in a spatially-defined depletion region at the surface of the semiconductor. The formation of the potential well is controlled by the manipulation of voltages applied to the surface electrodes, or gates. The charge packets are transferred to similar adjacent wells by providing a more attractive potential for the charge in the desired direction. Clocking signals having different phases and/or voltage levels are applied to the gates and are used to control the potential wells.
A second type of CCD is called a buried channel device, as opposed to a surface channel device. In buried channel CCDs, a channel implanted within the silicon surface is used to help transfer the charge packets. Therefore, the charge is located within the bulk silicon such that the potential maximum does not occur at the surface of the semiconductor device. Since the fringing fields are much greater below the surface, the charge transfer can be much faster. In addition, storing the charge away from the silicon/silicon-dioxide interface results in greatly improved charge transfer efficiency. Thus, an additional benefit of buried channel CCDs over surface channel CCDs is its low noise performance.
A third type of CCD is called a peristaltic CCD. In a peristaltic charge-coupled device, the charge packet transferring operation is similar to the peristaltic contractions and dilations of the digestive system. The peristaltic CCD has an additional implant that not only keeps the charge away from the silicon/silicon-dioxide interface, but also generates an extremely large lateral electric field from one gate to the next. This provides an additional driving force to aide in transfer of the charge packets. When the charge packets are shifted out of the CCD, amplified, and applied to an analog-to-digital converter for digitization, an accurate electrical representation of the optical image is created.
A typical digitized image may be constructed from a 512.times.512 array containing approximately 250,000 pixels. Today's applications for solid state imagers require frame rates in excess of 1000 frames-per-second (fps) on imagers of 512.times.512 pixels or larger. The required optical bandwidth of the imagers must extend from infrared to ultraviolet radiation, i.e., 250-1000 nanometers (nm) wavelength. This high frame rate, combined with the large imager size and wide bandwidth requirements, presents very demanding specifications which are quite difficult and costly to achieve.
One of the major problems in building high-speed imagers is how to quickly transfer the electrical signal out of the imager. By dividing the imager into a number of sections, and by using multiple output structures, the imager performance can be dramatically increased. However, present-day CCD and silicon metal-oxide-semiconductor (MOS) technology severely limits the maximum speed with which the imager can output data.
Another problem with high-speed imagers lies with the photodetector. Two types of photodetectors are commonly used in solid state imaging arrays, i.e., the MOS capacitor and the P-N junction photodiode. The major difference between the two types of photodetectors is apparent in their optical bandwidths. The polysilicon gates overlying the active regions of the MOS photosite become opaque at optical wavelengths of less than approximately 450 nm. Since the P-N junction photodiode is not covered by a polysilicon gate, its optical bandwidth can extend down to 200 nm. However, the P-N Junction photodiode has other problems. When transferring photo-generated charge from the active photosite into the CCD shift register, the charge transfer process is not 100% complete, i.e., some of the signal electrons cannot be transferred during the required transfer period and remain in the photodiode. This incomplete transfer of the charge packet produces an effect known as image lag, which manifests itself as a smearing of the image. The problems associated with image lag become increasingly apparent as the imager's frame rate is increased.
A further problem occurs when the photodetector is illuminated by a scene in which certain regions are exposed to more intense radiation than other regions. The photodetector often becomes overloaded and produces excess charge which tends to spread out throughout the CCD channel. This charge spreading is exhibited as a blooming or blurring of the image. A common approach to blooming control is to provide an overflow drain in the channel stops of the CCD, which collect the excess charge. However, prior antiblooming techniques have not proven successful for high-speed imagers having a wide dynamic range of sensitivity.
A need, therefore, exists to provide a high-speed 512.times.512 imager which overcomes these deficiencies in the prior art.